Instruction-Level Microprocessor Modeling of Scientific Applications

Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized, cache-friendly codes. Where cycles are lost is the topic of much research. In this paper we attempt to model architectural effect on processor utilization with and without memory influence. By presenting analytical formulas that use measurements from "on-chip" performance counters, we provide a novel technique for modeling state-of-theart microprocessors over ASCI representative scientific applications. ASCI is the Accelerated Strategic Computing Initiative sponsored by the US Department of Energy. We derive formulas for calculating a lower bound for CPI0, CPI without memory effect, and we quantify utilization of architectural parameters. These equations are architecturally diagnostic and qualitatively predictive in nature. Results provide promise in code characterization, and empirical/analytical modeling.